Block decoded wordline driver with positive and negative voltage modes

ABSTRACT

The negative supply voltage used by the drivers during sector or chip level erase operations is decoded separately from the decoding of the inputs of the individual wordline drivers in a compact wordline driver and decoder system. An integrated circuit memory comprising an array of memory cells arranged in a plurality of segments, a set of wordlines is coupled to the memory cells in the array, and wordline driver circuitry coupled to the set of wordlines is provided. The wordline driver circuitry includes a first supply voltage source, a second supply voltage source, and a set of wordline drivers. The wordline drivers are coupled to the first and second supply voltage sources, and selectively drive wordlines in the set of wordlines with a wordline voltage from either the first supply voltage source or the second supply voltage source in response to address signals which identify the respective drivers. The second supply voltage source includes a set of supply voltage selectors. Each supply voltage selector in the set is coupled with a subset of the set of drivers. The subset of drivers is coupled with a respective segment in the array. The supply voltage selectors select a negative erase supply voltage or an erase inhibit supply voltage during an erase mode in response to address signals identifying the respective segments. The selected negative erase supply voltage or erase inhibit supply voltage is applied to the subsets of the set of drivers which are coupled to the respective segment on a segment by segment basis.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to wordline drivers used in memory arrayswhich are capable of driving both positive and negative voltages on thewordlines; and more particularly to floating gate memory devices whichapply a negative voltage to wordlines during an erase mode, and apositive voltage to individual wordlines during a read mode and aprogram mode.

2. Description of Related Art

In nonvolatile semiconductor memory devices based on floating gatememory cells, such as those known as flash EEPROM, positive and negativevoltages are used to read and write data into the nonvolatile memoryarray. The writing of data into the nonvolatile memory array forfloating gate devices involves processes known as the program and erasemodes. The erase mode involves setting an entire array, or at least asector of an array, to a single state, in which either all of the cellsin the array (or sector) have a low threshold or all of the cells in thearray (or sector) have a high threshold. Whether the erased state is ahigh threshold state, in which the floating gate of the cell is chargedor a low threshold state in which the floating gate is discharged,depends on the particular implementation of the flash memory. Theprogramming mode involves charging or discharging the floating gate ofindividually addressed cells in the array to establish the oppositethreshold level with respect to the erased state.

It is well known that in order to discharge the floating gate, it isadvantageous to apply a negative voltage to the wordline for the cell tobe discharged. This assists in driving electrons out of the floatinggate into the source, drain or channel regions of the cell, which aretypically biased to a positive level to attract the electrons. However,circuitry for applying a negative voltage to a wordline presents somedifficulties.

Wordline drivers must be capable of driving a positive voltage during anormal read mode for the device to selected wordlines in response todecoded addresses. It has proved difficult in the prior art to provide awordline driver with the simple circuitry that can also apply a negativevoltage to selected the wordlines. Prior systems for applying negativevoltages to the wordlines have overridden the decoding function whichdrives the wordline driver, making it impossible to selectively applynegative voltages to individual wordlines. See, for instance, EuropeanPatent Application No. 92112727.0 entitled NONVOLATILE SEMI-CONDUCTORMEMORY DEVICE HAVING ROW DECODER, invented by Atsumi, et al.(Publication No. 0 525 678 A2); and European Patent Application No.92830115.9, entitled DECODER CIRCUIT CAPABLE OF TRANSFERRING POSITIVEAND NEGATIVE VOLTAGES, invented by Gastaldi (Publication No. 0 559 995A1). In both of these European patent applications, a wordline driver isdisclosed which provides a positive voltage to selected wordlines fornormal read mode operations, but overrides the selecting function of thedecoder during an erasing mode to apply a negative voltage to allwordlines. Because the decoding function is overridden, negativewordline voltages are applied to circuitry for all cells, even during asector erase. This results in disturbance of cells that are not beingerased.

In alternative systems, separate drivers, one for positive voltage andone for negative voltage, at opposite ends of the wordline and eachcoupled to the decoding circuit have been used. For instance, Arakawa,U.S. Pat. No. 5,136,541, entitled PROGRAMMABLE READ ONLY MEMORY USINGSTACKED-GATE CELL ERASABLE BY HOLE INJECTION, and Arakawa, U.S. Pat. No.5,253,200 entitled ELECTRICALLY ERASABLE AND PROGRAMMABLE READ ONLYMEMORY USING STACKED-GATE CELL, describe a system for driving a wordlinewith a positive and negative voltage based on the use of separatedrivers. (See, for instance, FIG. 3 of Arakawa's U.S. Pat. No.5,136,541).

U.S. Pat. No. 5,331,480 entitled METHOD AND APPARATUS FOR EPROM NEGATIVEVOLTAGE WORDLINE DECODING, invented by Schreck, describes a system inwhich each wordline has an independent negative voltage charge pump inorder to provide for decoding in a negative voltage and positive voltagestate. However, when a single negative voltage source is coupled to aplurality of wordline drivers, all wordlines are driven negative at thesame time. Thus, the Schreck circuit is impractical in large memorysystems because of the expense and complexity in repeating large numbersof charge pumps on a single chip.

Venkatesh, et. al., "A55 ns 6.35 μm 5V-only 16M Flash Memory withDeep-Power-Down," 1996, IEEE International Solid-State CircuitsConference, Paper JP 2.7, pp. 44-45; discloses a wordline driver forpositive and negative voltages (FIG. 1(a)), and mentions sector erase.However, there is no discussion of decoding of the wordlines duringerase. See also U.S. Pat. No. 5,521,867 (FIG. 4), entitled ADJUSTABLETHRESHOLD VOLTAGE CONVERSION CIRCUIT, invented by Chen, et. al.

It is desirable to provide a simplified wordline driver capable ofselectively applying positive or negative voltages to a wordline duringa program mode in a floating gate device, or otherwise to the wordlinein a memory array. It is further desirable that the driver be small inlayout, and support sector level erase operations in which the wordlinesof memory cells in the block to be erased are driven with negativevoltages.

SUMMARY OF INVENTION

The present invention provides a compact wordline driver and decodersystem in which the negative supply voltage used by the wordline driversduring sector or chip level erase operations is decoded separately fromthe decoding of inputs to the individual wordline drivers. This allowsfor use of wordline drivers having a small layout, yet maintaining theability to decode the negative voltage driving capability at the sectorlevel. Also, this design minimizes the number of so called triple welltransistors which are required for implementation of high negativevoltage circuits on an integrated circuit of this nature. Accordingly,using the wordline driver of the present invention, an integratedcircuit memory is provided with compact array layout and thereforereduced cost.

Thus, the present invention can be characterized as an integratedcircuit memory comprising an array of memory cells arranged in aplurality of segments. A set of wordlines is coupled to the memory cellsin the array. Wordline driver circuitry is coupled to the set ofwordlines. The wordline driver circuitry includes a first supply voltagesource, a second supply voltage source, and a set of wordline drivers.The wordline drivers are coupled to the first and second supply voltagesources, and selectively drive wordlines in the set of wordlines with awordline voltage from either the first supply voltage source or thesecond supply voltage source in response to address signals whichidentify the respective drivers. The individual drivers are connected tosets including one or more wordlines. The second supply voltage sourceincludes a set of supply voltage selectors. Each supply voltage selectorin the set is coupled with a subset of the set of drivers. The subset ofdrivers is coupled with a respective segment in the array. The supplyvoltage selectors select a negative erase supply voltage or an eraseinhibit supply voltage during an erase mode in response to addresssignals identifying the respective segments. The selected negative erasesupply voltage or erase inhibit supply voltage is applied to the subsetsof the set of drivers which are coupled to the respective segment on asegment by segment basis. This enables erase operations with a compactwordline driver design at a segment level, where a segment is a block orsector of the array that is coupled to more than one wordline driver,such as 16 wordline drivers.

According to one aspect of the invention, the wordline circuitryincludes logic that causes the drivers to select the second supplyvoltage source during the erase mode for all wordlines in the set ofwordlines. Such logic in one embodiment overrides the address signalsidentifying the respective drivers during the erase mode, in the logicwhich supplies the inputs to the drivers.

According to another aspect of the invention, the wordline driverscomprise an inverter having an input driven in response to addresssignals identifying the corresponding driver, a first supply terminalcoupled to the first supply voltage source, a second supply terminalcoupled to the second supply voltage source, and an output coupled toone or more wordlines in the set of wordlines. Also, a feedback circuitis included that is coupled between the output and the input of theinverter. In one embodiment, the inverter comprises a p-channel MOStransistor in series with a triple well n-channel MOS transistor. Thesource of the n-channel MOS transistor is coupled to the second supplyvoltage source, and supports transferring of the high negative voltageto the wordline. The source of the p-channel MOS transistor is coupledto the first supply voltage source, and supports applying positivevoltages to the wordline during the read and program modes. In anotheraspect, the feedback circuit comprises a p-channel MOS transistor havingits source coupled to the first supply terminal, its gate coupled to theoutput of the driver, and its drain coupled to the input of the driver.

According to another aspect of the invention, the present inventioncomprises a flash memory device comprising an array of floating gatememory cells. Control logic on the device establishes a read mode, aprogram mode and an erase mode. Wordline driver circuitry as describedabove is included on the device. The wordline driver circuitry includessegment decoder logic that is coupled to the drivers in the set ofdrivers. The segment decoder logic causes the inputs of the drivers tobe set in response to address signals identifying the drivers during theread mode so that they supply a read supply voltage to addressedwordlines. In the erase mode the decoder logic causes the inputs to thedrivers to be supplied independent of the address signals, and thesupply voltage selectors select a negative erase supply voltage or theerase inhibit voltage in response to address signals identifying therespective segments.

In a preferred floating gate memory architecture, the negative erasesupply voltage has a value in the range of -5 to -10 volts such as about-8 volts, while the erase inhibit supply voltage has a value in therange of +3 volts to -3 volts, and preferably about ground potential.The cells in the array are otherwise biased in this condition to induceFowler Nordheim tunneling in the floating gate memory cells in thesegment being erased.

Alternatively, the present invention can be characterized as a wordlinedriver in a set of wordline drivers. The wordline driver according tothis aspect comprises a first supply voltage source and a second supplyvoltage source. The second supply voltage source includes a supplyvoltage selector which selects a negative voltage or an inhibit supplyvoltage as a second supply voltage in response to a supply selectsignal. Decode logic, responsive to address signals identifying thedriver and a mode signal, operates to supply a decode logic output inresponse to the address signals when the mode signal is in a firststate, and without response to the address signals when the mode signalis in a second state. Supply select logic is responsive to addresssignals identifying a plurality of wordline drivers in the set ofwordlines, such as a plurality of wordline drivers corresponding to asegment of the memory to be erased. The supply select logic supplies thesupply select signal without response to the address signals when themode signal is in a first state, and in response to the address signalswhen the mode signal is in the second state. The driver further includesan inverter having an input coupled to the decode logic output, a firstsupply terminal coupled to the first supply voltage source, a secondsupply terminal coupled to the second supply voltage source to receivethe second supply voltage, and an output coupled to a wordline. Afeedback circuit is coupled between the output and the input of theinverter. In preferred aspects, the inverter and feedback circuit areimplemented as discussed above.

Accordingly, the present invention provides a set of wordline driversfor a memory organized into a plurality of segments. The wordlinedrivers in a given segment share the same second supply voltage sourcewhich is capable of applying a negative voltage. Thus each segment hasits own second supply voltage source. Under this arrangement, thewordline drivers within one segment experience either a negative voltageon the second supply terminal or a inhibit voltage such as ground on thesecond supply terminal. Under this approach, a simplified wordlinedriver and compact overall array architecture are achieved.

Accordingly, the present invention provides a compact decoded wordlinedriver which can be used in a flash EEPROM device for providing positiveand negative decode modes. This system is small, operates with greatefficiency, and eliminates complex circuitry of prior art systems.

Other aspects and advantages of the present invention can be seen uponreview of the figures, the detailed description and the claims whichfollow.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a schematic diagram of a Flash EEPROM device including adecoder with positive and block decoded negative voltage wordlinedrivers according to the present invention.

FIG. 2 is an illustration of a Flash EEPROM array for use in the deviceof FIG. 1.

FIG. 3 is a schematic diagram of a wordline driver according to thepresent invention.

FIG. 4 illustrates isolated n-channel transistor which is used in thedriver of FIG. 3.

FIG. 5 illustrates a supply voltage selector for selecting between anegative voltage and a ground voltage or other inhibit level voltage.

FIG. 6 made up of FIGS. 6A-6C illustrates a layout of the wordlinedecoding system according to the present invention.

DETAILED DESCRIPTION

A detailed description of preferred embodiments of the present inventionis provided with reference to FIGS. 1-6.

In FIG. 1, a flash device is shown, which includes a floating gatetransistor array 100 having a plurality of sectors capable ofindependently being erased, which might be implemented as shown in FIG.2. Coupled to the array are a decoder 101, which has positive and blockdecoded negative voltage wordline drivers. A mode control circuit 106 iscoupled to the negative voltage generator 108, positive voltagegenerator 109, and column and virtual ground decoders 105 to provide aread RD, a program PGM, and an erase ERS mode for the Flash device. Anegative voltage generator 108 and a positive voltage generator 109 arealso coupled with the decoder.

Column and virtual ground decoders 105 are coupled to the bitlines inthe array as shown, and to the negative voltage generator 108 andpositive voltage generator 109. Finally, sense amps 107 and programdata-in structures 103 are coupled to the column and virtual grounddecoders 105 for use in programming and reading the array.

FIG. 2 illustrates one embodiment of a flash memory array which might beused with the system of FIG. 1. FIG. 2 shows two pairs of columns of thearray, where each pair of columns includes flash cells in adrain-source-drain configuration.

Thus, the first pair 120 of columns includes a first drain diffusionline 121, a source diffusion line 122, and a second drain diffusion line123. Wordlines WL0 through WL63 each overlay the floating gates of acell in a first one of the pairs of columns and a cell in the second oneof the pairs of columns. As shown in the figure, a first pair 120 ofcolumns includes one column including cell 124, cell 125, cell 126, andcell 127. Not shown are cells coupled to wordlines WL2 through WL61. Thesecond one of the pair 120 of columns includes cell 128, cell 129, cell130, and cell 131. Along the same column of the array, a second pair 135of columns is shown. It has a similar architecture to the pair 120 ofcolumns except that it is laid out in a mirror image.

Thus, as can be seen, the transistor in the first one of the pair ofcolumns, such as the cell 125, includes a drain in drain diffusion line121, and a source in the source diffusion line 122. A floating gateoverlays the channel region between the first drain diffusion line 121and the source diffusion line 122. The wordline WL1 overlays thefloating gate of the cell 125 to establish a flash cell.

The column pair 120 and column pair 135 share an array virtual grounddiffusion 136 (ARVSS). Thus, the source diffusion line 122 of columnpair 120 is coupled to the ground diffusion 136. Similarly, the sourcediffusion line 137 of column pair 135 is coupled to the ground diffusion136.

As mentioned above, each pair 120 of columns of cells shares a singlemetal line. Thus, a block right select transistor 138 and a block leftselect transistor 139 are included. The transistor 139 includes a sourcein the drain diffusion line 121, a drain coupled to a metal contact 140,and a gate coupled to the control signal BLTR1 on line 141. Similarly,the right select transistor 138 includes a source in the drain diffusionline 123, a drain coupled to the metal contact 140, and a gate coupledto the control signal BLTR0 on line 142. Thus, the select circuitry,including transistors 138 and 139, provides for selective connection ofthe first drain diffusion line 121 and a second drain diffusion line 123to the metal line 143 (MTBL0) through metal contact 140. As can be seen,column pair 135 includes left select transistor 144 and right selecttransistor 145 which are similarly connected to a metal contact 146.Contact 146 is coupled to the same metal line 143 as is contact 140which is coupled to column pair 120. The metal line can be shared bymore than two columns of cells with additional select circuitry.

Column pairs are laid out horizontally and vertically to provide anarray of flash cells comprising M wordlines and 2N columns. The arrayrequires only N metal bit lines each of which is coupled to a pair ofcolumns of flash cells through select circuitry, as described above.

Although the figure only shows four sub-blocks 120, 135, 150, and 151,coupled to two metal bit lines 143 and 152 (MTBL0-MTBL1), the array maybe repeated horizontally and vertically as required to establish a largescale flash memory array. Thus, column pairs 120 and 150 which share awordline are repeated horizontally to provide a sector of the array.

Of course, the array architecture illustrated in FIG. 2 is one exampleof the kinds of non-volatile memory architectures with which the presentinvention may be used. A variety of other architectures are also suitedto segmented erase operations, and would benefit from the presentinvention.

FIG. 3 illustrates a preferred embodiment of the wordline driveraccording to the present invention. The wordline driver includes a firstsupply voltage source (such as positive voltage generator 109 of FIG. 1)which is connected to the AVX terminal 300. Also a second supply voltagesource is coupled to terminal 301, which supplies a high voltage driverV_(SS) voltage HVDRVSS. The second supply voltage source includes asupply voltage selector 302 which selects a negative voltage NVPP fromterminal 303 or an inhibit supply voltage HVDRGND on terminal 304 asoutput in response to a supply select signal on line 315. In a preferredsystem, the value of NVPP is about -8 volts, and typically falls withinthe range of -5 to -10 volts. The value of HVDRGND is preferably aboutground potential or 0 volts, and typically falls within the range ofabout -3 volts to +3 volts.

A positive supply voltage AVW is applied on line 305 to the selector302. This positive supply voltage AVW (same as AVX during erase mode,about 3 volts) is controlled as discussed below during operation of theselector 302. The voltage HVDRVSS on line 301 is shared among aplurality of driver circuits 306, as indicated by the arrow 317.

The core driver circuit 306 includes an inverter composed of transistorsMP3 and MT0 having their gates coupled to an input at node 307, andtheir drains coupled to a wordline or a set of wordlines 308. The drivercircuit 306 also includes feedback which is provided by p-channeltransistor MP0 which has its gate coupled to the output 308, its draincoupled to the input 307, and its source coupled to the supply terminal300. The n-wells of the p-channel transistors MP0 and MP3 are bothcoupled to the AVX supply terminal 300.

The n-channel transistor MT0 consists of a triple well transistorimplemented as shown in FIG. 4. This structure will be described below.The deep n-well is biased at the supply potential V_(DD) which istypically 5 volts±10% and serves to isolate the n-channel transistorfrom the p-type substrate during negative voltage operations. In someembodiments, the supply voltage V_(DD) is lesser or greater as suits aparticular implementation. The driver circuit 306 also includes a"keeper" transistor MN2 which consists of a n-channel transistor havingits source coupled to the input 307 its drain coupled to the supplyterminal V_(DD), and its input coupled to a control signal XDHB on line309. This control signal XDHB on line 309 is controlled during negativevoltage operations as discussed below.

Also, an n-channel transistor MN1 is connected in a pass-gateconfiguration between the input 307 and further decode logic representedby NAND gate 310. The n-channel transistor MN1 has its gate coupled tothe signal XR on line 312 which is supplied by the wordline decodinglogic. The source of transistor MN1 is connected to the output of theNAND gate 310. The inputs to the NAND gate include the signals XP, XBL2,and XBL3 derived from address signals. These signals in combination withthe decode signal XR on line 312 serve to identify the particular drivercircuit 306. Another input to the NAND gate 310 comprises a mode signalERASEB which is low during the erase mode. Thus, during the erase mode,the signals derived from the address signals are overridden and theinput on line 307 of the wordline circuit 306 is driven to a logic 1value when XR is high.

Thus, the input on line 307 is driven in response to address signalsidentifying a particular driver during the read and program modes.However, the address signals are overridden during the erase mode andthe driver circuit 306 receives a logic 1 value for all wordlines in aset of wordlines coupled to this decoding system. The signal XR is highon all drivers, in this example. On the other hand, the supply selectsignal on line 315 at the input to supply voltage sector 302 is drivenby the NAND gate 311. The inputs to the NAND gate 311 include thesignals XBL2 and XBL3 derived from the address signals, and the erasemode signal ERASE. During the erase mode, the signal ERASE is highenabling the output of the NAND gate 311 to be controlled by the addresssignals XBL2 and XBL3 which identify a particular segment of the array.These signals XBL2 and XBL3 are the same signals XBL2 and XBL3 which areapplied to the input of NAND gate 310 which drives each of the wordlinedriver circuits 306 in the segment being selected.

In another alternative logic design, the NAND gate 310 is simplified toa 3 input NAND gate, removing the control signal ERASEB as input. Thesignal XR is controlled in response to ERASEB or its equivalent todisconnect the drivers from the gate 310, while XDHB is driven to alevel that applies a logic one to node 307 without driving node 307 to alevel exceeding AVX during erase mode.

Accordingly, the wordline driver operates during the read and programmode to apply a positive voltage from the supply AVX, or ground as aresult of the specific wordline circuit 306 being activated by thewordline decoding system. During erase, a negative voltage or ground isapplied to the wordline through the triple well n-channel transistorMN0. The operation conditions of the wordline driver circuit 306 areshown in Table 1 which follows:

    ______________________________________                                        Operation Mode XDHB       HVDRVSS    AVX                                      ______________________________________                                        READ           VDD        0 v        Vcc                                      Programming                       0 v VDD                                                                                12 v                               Programming Inhibit of Row                                                                           VDD                                                                                      0 v                                                                                    12 v                               Erase of blocks                                                                                         -8 v -->0 v                                                                                3 v                                    Erase Inhibit of blocks                                                                           VDD-->0 v                                                                           0 v              3 v                                ______________________________________                                    

U.S. Pat. No. 5,463,586 is incorporated by reference as if fully setforth herein, for the description of a suitable supply voltage selectorfor the positive voltage AVX. A wide variety of implementations of suchsupply voltage selector are suitable for utilization according to thepresent invention.

During the erase mode, the control signal XDHB is switched from V_(DD)to 0 volts in order to break the connection between the terminal AVX online 300 and the supply voltage V_(DD). Alternatively, XDHB is driven toa level that prevents node 307 from exceeding AVX, as mentioned above.

It will be appreciated that wordline driver circuits 306 which have thesame XBL2 and XBL3 but have different XP and XR share the same supplyvoltage selector 302. As a result, the wordline drivers in a segment ofthe floating gate memory array are switched to the negative voltagetogether.

A description of the triple well n-channel MOS transistor MT0 isillustrated in FIG. 4. The supply voltage selector 302 in a preferredembodiment is illustrated in FIG. 5, and the modified wordline decodingsystem according to the present invention is illustrated in FIG. 6.

The structure for a triple well n-channel transistor such as MT0 isillustrated in FIG. 4. In particular, the transistor is composed of agate terminal 400 over a channel region 401 which is formed betweenn-type diffusion regions 402 and 403 operating as the drain and source,respectively, of the transistor. The n-type diffusion regions 402 and403 are implemented in the isolated p-type well 404. The p-type well hasa contact at point 405 which is connected to the HVDRVSS value on line301.

The p-type well 404 is, in turn, formed in an n-type well 406, which hascontact 407 to a positive supply voltage V_(DD). The n-type well 406 is,in turn, formed in a p-type substrate 408. The structure establishes ap-n junction, schematically represented by the diode symbol 409 betweenthe p-well 404 and the n-well 406. When negative voltages are applied tothe p-well 404, this junction is reversed biased, isolating the n-wellfrom the negative voltage. Similarly, a p-n junction represented by thediode symbol 410 is formed between the p-type substrate and the n-well406. By biasing the n-well 406 with a positive voltage, this junction410 is reversed biased, isolating the entire structure from thesubstrate.

FIG. 5 illustrates the supply voltage selector 302 of FIG. 3 in onepreferred embodiment. The supply voltage selector receives a supplyinput AVW on line 500, and selector signal ENB on line 501, a negativevoltage NVPP on line 502, and a ground voltage HVDRGND on line 503. Thecircuit operates to select between the negative voltage 502 and theground voltage 503 for supply on an output 504 which corresponds to thesignal HVDRVSS on line 301 of FIG. 3. The supply selector includesp-channel MOS transistor MP1 which has its source and n-well coupled tothe supply terminal 500, its gate coupled to line 501, and its draincoupled to node 510. P-channel MOS transistor MP2 has its source andn-well coupled to node 500, its gate connected to the output of aninverter 511 which has its input connected to node 501. The drain oftransistor MP2 is connected to node 512. A triple well n-channel MOStransistor MT3 has its gate connected to node 512, its drain connectedto node 510, its source and p-well connected to terminal 502 at whichthe negative voltage is applied. The deep n-well is coupled to thesupply terminal V_(DD). Triple well transistor MT4 has its drain coupledto node 512, its gate coupled to node 510, and its source coupled tonode 502. Also, the p-well of transistor MT4 is also coupled to node502. The deep n-well of transistor MT4 is coupled to the supply terminalV_(DD).

Node 512 is coupled to the source of triple well transistor MT1 whichhas its gate coupled on line 513 to a ground potential and its draincoupled to the output node 504. The p-well of triple well transistor MT1is coupled to node 502, while the deep n-well is coupled to the supplyterminal V_(DD). Triple well transistor MT2 has its gate coupled to node512, its source coupled to the ground terminal 503, its p-well coupledto node 502, and its deep n-well coupled to the positive supply terminalV_(DD). The drain of transistor MT2 is coupled to the output node 504.

In operation, as the select signal ENB on line 501 is low, node 512 isdriven to the negative voltage NVPP via transistor MT4. This negativevoltage, typically -8 volts, is thus applied to node 504 throughtransistor MT1 and transistor MT2 is turned off. Transistor MT2 servesto isolate the negative voltage at node 504 from the ground potential onnode 503.

When the input signal ENB on line 501 is driven to the supply voltageV_(DD), the node 512 is driven to the AVW value (typically 3 volts). TheAVW value turns on transistor MT2, and causes transistor MT1 to turnoff. This supplies the ground potential at line 503 to the output onnode 504, while isolating the node 504 from the voltage at node 512.

FIG. 6 illustrates the wordline decoding system including the supplyvoltage selector of the present invention. The wordline decoding systemof FIG. 6 corresponds to the decoding system for a segment of the arraywhich drives 16 wordlines including wordlines WLL0-WLL7 on the left andwordlines WLR0-WLR7 on the right. Each of the wordlines is driven by awordline driver circuit 306 as described in FIG. 3. The inputs to thewordline driver circuits 306 include the values AVX, XDHB. Also, each ofthe drivers 306 receives an input from the decoding system labeled inthe system XRL0-XRL7 on the left, and XRR0-XRR7 on the right.

The input to each of the wordline circuits is supplied at the output ofthe NAND gate 310, which corresponds to the NAND gate of FIG. 3. Thewordline circuits also receive the HVDRVSS signal the output of thewordline selector 302.

According to this embodiment, the XP signal is one of four XP signals(XP10-XP13) generated in response to the address signals. The XBL2signal is one of four (XBK20-XBL23), and the XBL3 signals is one ofeight (XBL30-XBL37). The XBL2 signal and XBL3 signal supplied at theinput of NAND gate 311 are the same as those applied to the input ofNAND gate 310 for a single segment of the array.

Accordingly, an efficient compact wordline driver circuitry supporting asegment erase operation for floating gate memory devices such as flashmemory has been provided. The circuit reduces the layout and complexityrequired for negative voltage decoding, and overall reduces the cost ofintegrated circuits implementing this feature.

The foregoing description of a preferred embodiment of the invention hasbeen presented for purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formsdisclosed. Obviously, many modifications and variations will be apparentto practitioners skilled in this art. It is intended that the scope ofthe invention be defined by the following claims and their equivalents.

What is claimed is:
 1. An integrated circuit memory, comprising:an array of memory cells arranged in a plurality of segments; a set of wordlines coupled to memory cells in the array; wordline driver circuitry coupled to the set of wordlines, including a first supply voltage source, a second supply voltage source, and a set of drivers, coupled to the first and second supply voltage sources, the drivers in the set of drivers selectively driving wordlines in the set of wordlines with a wordline voltage from the first supply voltage source or the second supply voltage source in response to address signals identifying the respective drivers; wherein the second supply voltage source includes a set of supply voltage selectors coupled with subsets of the set of drivers for respective segments of the array, which select a negative erase supply voltage or an erase inhibit supply voltage during an erase mode in response to address signals identifying the respective segments to the respective subsets of the set of drivers.
 2. The integrated circuit memory of claim 1, wherein the wordline driver circuitry includes logic that causes the drivers in the set of drivers to select the second supply voltage source during the erase mode for all wordlines in the set of wordlines.
 3. The integrated circuit memory of claim 2, wherein the wordline driver circuitry includes logic that overrides the address signals identifying the respective drivers during the erase mode.
 4. The integrated circuit memory of claim 1, wherein the drivers in the set of drivers comprisean inverter, having an input driven in response to address signals identifying the driver, a first supply terminal coupled to the first supply voltage source, a second supply terminal coupled to the second supply voltage source, and an output coupled to a wordline in the set of wordlines; and a feedback circuit, coupled between the output and the input of the inverter.
 5. The integrated circuit memory of claim 4, wherein the inverter comprisesa p-channel MOS transistor in a substrate having a source coupled to the first supply terminal, a gate coupled to the input, and a drain coupled to the output of the driver; an n-channel MOS transistor in the substrate having a source coupled to the second supply terminal, a gate coupled to the input, and a drain coupled to the output of the driver, the n-channel MOS transistor having a p-type channel region in a deep n-type well biased for isolating the channel region from the substrate.
 6. The integrated circuit memory of claim 5, wherein the feedback circuit comprisesa p-channel MOS transistor in a substrate having a source coupled to the first supply terminal, a gate coupled to the output, and a drain coupled to the input of the driver.
 7. The integrated circuit memory of claim 1, wherein the negative erase supply voltage has a value in the range of negative 5 to negative 10 volts.
 8. The integrated circuit memory of claim 1, wherein the negative erase supply voltage has a value in the range of negative 5 to negative 10 volts, and the erase inhibit supply voltage has a value in the range of negative 3 to positive 3 volts.
 9. The integrated circuit memory of claim 1, wherein the wordline driver circuitry includes segment decoder logic coupled to drivers in the set of drivers, the segment decoder logic having a read mode in which inputs to the drivers in the set are supplied in response to the address signals identifying the drivers and the supply voltage selector coupled with the segment selects a read supply voltage, and a segment erase mode in which inputs to the drivers in the subsets of the set of drivers for respective segments are supplied in response to an erase mode signal, and the supply voltage selectors coupled with the respective segments select the negative erase supply voltage or the erase inhibit supply voltage in response to address signals identifying the respective segments.
 10. An integrated circuit memory, comprising:an array of floating gate memory cells arranged in a plurality of segments; control logic, coupled to the array, establishing a read mode, a program mode and an erase mode; a set of wordlines coupled to memory cells in the array; wordline driver circuitry coupled to the set of wordlines and the control logic, including a first supply voltage source, a second supply voltage source, and a set of drivers, coupled to the first and second supply voltage sources, the drivers in the set of drivers selectively driving wordlines in the set of wordlines with a wordline voltage from the first supply voltage source or the second supply voltage source in response to address signals identifying the respective drivers in the read mode and the program mode; wherein the second supply voltage source includes a set of supply voltage selectors coupled with subsets of the set of drivers for respective segments of the array, which select a negative erase supply voltage or an erase inhibit supply voltage during the erase mode in response to address signals identifying the respective segments to the respective subsets of the set of drivers.
 11. The integrated circuit memory of claim 10, wherein the wordline driver circuitry includes logic that causes the drivers in the set of drivers to select the second supply voltage source during the erase mode for all wordlines in the set of wordlines.
 12. The integrated circuit memory of claim 11, wherein the wordline driver circuitry includes logic that overrides the address signals identifying the respective drivers during the erase mode.
 13. The integrated circuit memory of claim 10, wherein the drivers in the set of drivers comprisean inverter, having an input driven in response to address signals identifying the driver, a first supply terminal coupled to the first supply voltage source, a second supply terminal coupled to the second supply voltage source, and an output coupled to a wordline in the set of wordlines; and a feedback circuit, coupled between the output and the input of the inverter.
 14. The integrated circuit memory of claim 13, wherein the inverter comprisesa p-channel MOS transistor in a substrate having a source coupled to the first supply terminal, a gate coupled to the input, and a drain coupled to the output of the driver; an n-channel MOS transistor in the substrate having a source coupled to the second supply terminal, a gate coupled to the input, and a drain coupled to the output of the driver, the n-channel MOS transistor having a p-type channel region in a deep n-type well biased for isolating the channel region from the substrate.
 15. The integrated circuit memory of claim 14, wherein the feedback circuit comprisesa p-channel MOS transistor in a substrate having a source coupled to the first supply terminal, a gate coupled to the output, and a drain coupled to the input of the driver.
 16. The integrated circuit memory of claim 10, wherein the negative erase supply voltage has a value in the range of negative 5 to negative 10 volts.
 17. The integrated circuit memory of claim 10, wherein the negative erase supply voltage has a value in the range of negative 5 to negative 10 volts, and the erase inhibit supply voltage has a value in the range of negative 3 to positive 3 volts.
 18. The integrated circuit memory of claim 10, wherein the wordline driver circuitry includes segment decoder logic coupled to drivers in the set of drivers, the segment decoder logic causing inputs to the drivers in the set to be supplied in response to the address signals identifying the drivers so that the drivers select a read supply voltage in the read mode, and causing inputs to the drivers in the subsets of the set of drivers for respective segments to be supplied independent of the address signals in the erase mode, and the supply voltage selectors coupled with the respective segments to select the negative erase supply voltage or the erase inhibit supply voltage in response to address signals identifying the respective segments in the erase mode.
 19. A wordline driver in a set of wordline drivers, comprising:a first supply voltage source, and a second supply voltage source, the second supply voltage source including a supply voltage selector which selects a negative voltage or an inhibit supply voltage as a second supply voltage in response to a supply select signal; decode logic, responsive to address signals identifying the driver and a mode signal, to supply a decode logic output in response to the address signals when the mode signal is in a first state and without response to the address signals when the mode signal is in a second state; supply select logic, responsive to address signals identifying a plurality of wordline drivers in the set of wordline drivers, to supply the supply select signal without response to the address signals when the mode signal is in the first state and in response to the address signals when the mode signal is in the second state; an inverter, having an input connected to the decode logic output, a first supply terminal coupled to the first supply voltage source, a second supply terminal coupled to the second supply voltage source to receive the second supply voltage, and an output coupled to a wordline; and a feedback circuit, coupled between the output and the input of the inverter.
 20. The wordline driver of claim 19, wherein the inverter comprisesa p-channel MOS transistor in a substrate having a source coupled to the first supply terminal, a gate coupled to the input, and a drain coupled to the output of the driver; an n-channel MOS transistor in the substrate having a source coupled to the second supply terminal, a gate coupled to the input, and a drain coupled to the output of the driver, the n-channel MOS transistor having a p-type channel region in a deep n-type well biased for isolating the channel region from the substrate.
 21. The wordline driver of claim 20, wherein the feedback circuit comprisesa p-channel MOS transistor in a substrate having a source coupled to the first supply terminal, a gate coupled to the output, and a drain coupled to the input of the driver.
 22. The wordline driver of claim 19, wherein the negative voltage has a value in the range of negative 5 to negative 10 volts.
 23. The wordline driver of claim 19, wherein the negative voltage has a value in the range of negative 5 to negative 10 volts, and the inhibit supply voltage has a value in the range of negative 3 to positive 3 volts. 